| 引用本文: | 李传东,衣然,罗英伟,汪小林,王振林.RISC-V架构下的懒惰影子页表模型.软件学报,2025,36(9):3970-3984 |
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| RISC-V架构下的懒惰影子页表模型 |
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李传东1,2,3, 衣然1,2, 罗英伟1,2,3, 汪小林1,2,3, 王振林4
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1.北京大学 计算机学院, 北京 100871;2.多媒体信息处理全国重点实验室(北京大学), 北京 100871;3.中关村实验室, 北京 100094;4.Michigan Technological University, Houghton 49931-1295, USA
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| 摘要: |
| 内存虚拟化作为虚拟化技术的核心组成部分, 直接影响虚拟机的整体性能. 目前, 主流的内存虚拟化方法在两维地址翻译开销与页表同步开销之间面临权衡. 传统的影子页表模型通过一套由软件维护的页表, 实现了与原生(native)环境相当的地址翻译性能. 然而, 由于影子页表的同步依赖于基于写保护的机制, 频繁的虚拟机退出(VM-exit)会严重影响系统性能. 相对而言, 嵌套页表模型依靠硬件辅助虚拟化, 允许虚拟机的客户页表直接加载到内存管理单元中, 从而避免了页表同步的开销. 然而, 这种方法的两维页表遍历却显著降低了地址翻译效率. 基于RISC-V架构下的特权级模型和虚拟化硬件特性, 提出了一种懒惰影子页表模型LSP (lazy shadow paging), 在保留影子页表的地址翻译高效性的同时降低了页表同步开销. 懒惰影子页表模型深入分析了客户机对页表页的访问模式, 将页表同步与转址旁路缓存(translation lookaside buffer, TLB)刷新操作绑定以降低虚拟机退出的数量. 然后, 利用RISC-V架构中对TLB的细粒度刷新且可拦截的特性, 无效化需同步的影子页表项, 将页表同步的软件开销推迟到了首次访问该页面的时刻. 此外, 懒惰影子页表模型利用RISC-V架构中全新的特权级模型, 设计了TLB拦截的快速路径, 进一步减少了虚拟机退出带来的软件开销. 实验结果表明, 在基础RISC-V架构下, 懒惰影子页表相对于传统影子页表在微基准测试中降低了最多50%的虚拟机退出数量. 在支持RISC-V的虚拟化扩展架构下, 懒惰影子页表对SPEC2006基准测试中的典型应用相较于传统影子页表降低了最多25%的虚拟机退出数量, 相较于嵌套页表每次TLB缺失降低了12次访存. |
| 关键词: RISC-V 虚拟化扩展 内存虚拟化 影子页表 嵌套页表 |
| DOI：10.13328/j.cnki.jos.007359 |
| 分类号:TP316 |
| 基金项目:国家重点研发计划(2022YFB4500701); 国家自然科学基金(62032008, 62032001, 62372011) |
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| Lazy Shadow Paging Under the RISC-V Architecture |
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LI Chuan-Dong1,2,3, YI Ran1,2, LUO Ying-Wei1,2,3, WANG Xiao-Lin1,2,3, WANG Zhen-Lin4
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1.School of Computer Science, Peking University, Beijing 100871, China;2.National Key Laboratory for Multimedia Information Processing (Peking University), Beijing 100871, China;3.Zhongguancun Laboratory, Beijing 100094, China;4.Michigan Technological University, Houghton 49931-1295, USA
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| Abstract: |
| Memory virtualization, a core component of virtualization technology, directly impacts the overall performance of virtual machines. Current memory virtualization approaches often involve a tradeoff between the overhead of two-dimensional address translation and page table synchronization. Traditional shadow paging employs an additional software-maintained page table to achieve address translation performance comparable to native systems. However, synchronization of shadow page tables relies on write protection, frequently causing VM-exits that significantly degrade system performance. In contrast, the nested paging approach leverages hardware-assisted virtualization, allowing the guest page table and nested page table to be directly loaded into the MMU. While this eliminates page table synchronization, the two-dimensional page table traversal will seriously degrade the address translation performance. Two-dimensional page table traversal incurs substantial performance penalties for address translation due to privilege overhead. This study proposes lazy shadow paging (LSP), which reduces page table synchronization overhead while retaining the high efficiency of shadow page tables. Leveraging the privilege model and hardware features of the RISC-V architecture, LSP analyzes the access patterns of guest OS page tables and binds synchronization with translation lookaside buffer (TLB) flushes, reducing the software overhead associated with page table updates by deferring costs until the first access to a relevant page to minimize VM-exits. In addition, it introduces a fast path for handling VM-exits, exploiting the fine-grained TLB interception and privilege-level features of RISC-V to further optimize performance. Experimental results demonstrate that under the baseline RISC-V architecture, LSP reduces VM-exits by up to 50% compared to traditional shadow paging in micro-benchmark tests. For typical applications in the SPEC2006 benchmark suite, LSP reduces VM-exits by up to 25% compared to traditional shadow paging and decreases memory accesses per TLB miss by 12 compared to nested paging. |
| Key words: RISC-V hypervisor-extension memory virtualization shadow page table nested page table |
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