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| Spike-FlexiCAS: 支持缓存架构灵活配置的 RISC-V 处理器模拟器 |
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韩金池1,2, 王智栋1,2, 马浩1,2, 宋威1,2
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1.网络空间安全防御重点实验室 (中国科学院 信息工程研究所), 北京 100195;2.中国科学院大学 网络空间安全学院, 北京 101408
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| 摘要: |
| 缓存模拟器在缓存架构探索和缓存侧信道研究中起着不可或缺的作用. Spike作为RISC-V指令集的标准实现为基于RISC-V的缓存研究提供了完整的运行环境. 但Spike的缓存模型存在仿真粒度低, 与真实处理器的缓存结构差异大等诸多问题. 为此, 修改和扩展Spike的缓存模型并取名为FlexiCAS (flexible cache architectural simulator), 修改后的Spike称为Spike-FlexiCAS. FlexiCAS能支持多种缓存架构, 具有灵活配置、易扩展等特点并且可以对缓存特性(如一致性协议以及实现方式)进行任意的组合. 此外, FlexiCAS还能不依赖Spike单独地对缓存的行为进行模拟. 性能测试的结果表明, FlexiCAS对比当前最快的执行驱动型模拟器 ZSim的缓存模型具有明显的性能优势. |
| 关键词: 缓存架构 缓存侧信道 RISC-V 模拟器 |
| DOI：10.13328/j.cnki.jos.007358 |
| 分类号:TP316 |
| 基金项目:国家自然科学基金 (62172406); 中国科学院率先行动“百人计划” |
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| Spike-FlexiCAS: RISC-V Processor Simulator Supporting Flexible Cache Architecture Configuration |
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HAN Jin-Chi1,2, WANG Zhi-Dong1,2, MA Hao1,2, SONG Wei1,2
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1.Key Laboratory of Cyberspace Security Defense (Institute of Information Engineering, Chinese Academy of Sciences), Beijing 100195, China;2.School of Cyber Security, University of Chinese Academy of Sciences, Beijing 101408, China
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| Abstract: |
| Cache simulators are indispensable tools for exploring cache architectures and researching cache side channels. Spike, the standard implementation of the RISC-V instruction set, offers a comprehensive environment for RISC-V-based cache research. However, its cache model suffers from limitations, such as low simulation granularity and notable discrepancies with the cache structures of real processors. To address these limitations, this study introduces flexible cache architectural simulator (FlexiCAS), a modified and extended version of Spike’s cache model. The modified simulator, referred to as Spike-FlexiCAS, supports a wide range of cache architectures with flexible configuration and easy extensibility. It enables arbitrary combinations of cache features, including coherence protocols and implementation methods. In addition, FlexiCAS can simulate cache behavior independently of Spike. The performance evaluations demonstrate that FlexiCAS significantly outperforms the cache model of ZSim, the fastest execution-driven simulator available. |
| Key words: cache architecture cache side channel RISC-V simulator |
