With the rapid development of edge computing and intelligent end-side software, the RISC-V architecture attracts increasing attention in both academia and industry due to its open-source, modular, and low-cost characteristics. However, deploying intelligent software on the RISC-V architecture presents significant challenges. The execution of intelligent software relies on deep learning operators, such as convolution, matrix multiplication, and normalization. Once defects occur in these operators, the execution efficiency, accuracy, and reliability of a large number of upper-layer intelligent applications are directly affected, making operator quality evaluation critically important. Existing operator testing methods are primarily designed for x86 architectures and have difficulty characterizing the impact of varying computational complexity on RISC-V platforms under constraints such as limited memory capacity, power consumption, and system resources. To address this issue, this study proposes RIVdoo, a deep learning operator testing method tailored for the RISC-V architecture. RIVdoo systematically covers different computational workloads through a grouping strategy based on operator input-space complexity, evaluates accuracy, execution efficiency, memory usage, and system overhead using multidimensional metrics, and introduces a differential testing mechanism with complexity amplification factors to effectively identify performance anomalies and architectural adaptation issues. Experiments covering 47 operators across compute-intensive, memory-intensive, and lightweight categories demonstrate that RIVdoo reveals significant performance trade-offs and adaptation differences among existing operator libraries and optimization strategies on the RISC-V architecture. Specifically, TFLite trades 1.5×–2× memory overhead for 30%–50% performance improvement, which leads to memory bottlenecks in resource-constrained scenarios; TVM’s dynamic storage scheduling incurs 60%–150% higher page fault rates than TFLite due to the limited TLB and cache capacity of RISC-V; RVV vectorization causes performance degradation for certain operators and low-complexity workloads because of software emulation and startup overhead, indicating that existing optimization strategies lack targeted design for RISC-V platform characteristics. The results demonstrate that the runtime behavior of different operator implementations and optimization strategies on the RIVdoo architecture exhibits strong complexity-dependent characteristics, and that output correctness alone is insufficient to reflect real deployment performance. RISC-V provides a systematic evaluation methodology for operator adaptability analysis and optimization on RISC-V platforms.