Digital signature algorithms play a vital role in network security infrastructure. Most of the current digital signature schemes are based on RSA and ECC . With the rapid development of quantum computing technology, digital signature schemes based on traditional public key cryptography will face security risks. Researching and deploying new cryptographic schemes that can resist quantum attacks has become an important research direction. After several rounds of evaluation and analysis, NIST announced the post-quantum digital signature standard ML-DSA in August 2024, and its core algorithm is Dilithium. In view of the characteristics of the high-dimensional polynomial matrix operation of Dilithum, this paper proposes a variety of optimization implementation methods based on the FPGA platform, including multifunctional systolic array operation units with configurable parameters, dedicated polynomial parallel sampling modules, reconfigurable storage unit design for multiple parameter sets, and high-parallel timing state machines for complex multi-modules, aiming to break through performance bottlenecks and achieve higher signature operation efficiency, and finally realize a digital signature hardware architecture that can support three security levels at the same time. Our hardware architecture was actually deployed on the Xilinx Artix-7 FPGA platform, and compared with existing similar works. The results show that, our design has improved the signature operation efficiency by 7.4 times, 8.3 times and 5.6 times at three security levels, respectively, which will provide the performance foundation for quantum-resistant digital signature services, and provide meaningful application value and reference significance for the relevant research about lattice cryptography engineering and practicality.