| 引用本文: | 杨乐,刘晓义,李广力,渠鹏,崔慧敏,张悠慧.BIVM: 类脑计算编译框架及其原型研究.软件学报,2025,36(10):4768-4791 |
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| BIVM: 类脑计算编译框架及其原型研究 |
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杨乐1,2, 刘晓义1,2, 李广力3, 渠鹏1,2, 崔慧敏3, 张悠慧1,2,4
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1.清华大学 计算机科学与技术系, 北京 100084;2.清华大学 北京信息科学与技术国家研究中心, 北京 100084;3.中国科学院 计算技术研究所, 北京 100190;4.中关村实验室, 北京 100094
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| 摘要: |
| 各类新型架构的类脑计算芯片正不断涌现, 类脑神经网络训练/学习算法和高效的生物神经网络仿真也是研究热点. 但如何在架构迥异的类脑计算芯片上优化运行计算/访存特征不同的类脑应用是关键难点, 也是建立类脑计算良好生态环境的重点, 而通用计算领域的繁荣生态已经表明, 一个灵活、可扩展、可复用的编译框架是解决这一问题的有效途径. 为此提出BIVM, 一个类脑计算编译框架及其验证原型. BIVM基于领域定制化体系结构(domain specific architecture, DSA)的多层中间表示(multi-level intermediate representation, MLIR)框架, 设计了为类脑神经网络定制的多层 IR, 包括脉冲神经网络方言(高层 IR)、由 MLIR 内置方言为主组成的中间层 IR 和各类芯片的底层 IR. 针对不同类脑芯片的体系结构跨度很大且其提供的硬件功能粒度不一等问题, BIVM充分利用MLIR的progressivity特性, 所设计的IR能够混合不同的抽象层次和概念(比如混合细粒度指令与某些后端的以交叉开关结构为运算主体的粗粒度运算), 从而能够复用软件模块、简化开发; 在此基础上, 在多层IR的递降转换中灵活组合不同级别的编译优化方法, 包括被广泛采纳的SNN特定优化技术(如计算稀疏性挖掘与时空并行度挖掘)和适配目标硬件的底层优化技术, 以实现不同后端上的高性能. 目前, BIVM原型支持的后端有通用处理器(控制流架构)、具有控制流/数据流混合架构的脉冲神经网络加速芯片(FPGA), 以及基于ReRAM (resistive random-access memory, 阻变存储器)的数据流架构类脑芯片(软件仿真), 能够将智能应用与生物神经网络仿真应用优化编译为适配不同架构芯片的执行程序. 随后, 进行编译技术适配性分析与性能比较, 结果表明该类框架在编译高生产力、高可移植性、高性能方面具有良好潜力. |
| 关键词: 类脑计算 编译框架 类脑计算芯片 |
| DOI：10.13328/j.cnki.jos.007420 |
| 分类号:TP18 |
| 基金项目:国家自然科学基金面上项目(62072266); 国家自然科学基金原创探索计划 (62250006); 国家自然科学基金青年科学基金 (62202254); 北京信息科学与技术国家研究中心青年创新基金(BNR2022RC01003) |
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| BIVM: Compilation Framework for Brain-inspired Computing and Prototype Research |
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YANG Le1,2, LIU Xiao-Yi1,2, LI Guang-Li3, QU Peng1,2, CUI Hui-Min3, ZHANG You-Hui1,2,4
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1.Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China;2.Beijing National Research Center for Information Science and Technologu, Tsinghua University, Beijing 100084, China;3.Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China;4.Zhongguancun Laboratory, Beijing 100094, China
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| Abstract: |
| Brain-inspired computing chips of various architectures are emerging, and the inference/training/learning algorithms of spiking neural network (SNN) and the efficient simulation of biological neural networks have become research hotspots. Meanwhile, efficiently executing applications with different computation/memory-access characteristics on various chips remains a significant challenge, which is crucial for establishing a robust brain-inspired computing ecosystem. The success of the general-purpose computing ecosystem indicates that a flexible, scalable, and reusable compiler infrastructure is an effective solution to this problem. This study proposes BIVM, a compilation framework for brain-inspired computing, along with its proof-of-concept implementation. Based on the multi-level intermediate representation (MLIR) framework of domain specific architecture (DSA), multi-layer IRs customized for SNNs are designed, including an SNN dialect, middle-layer IRs composed mainly of MLIR’s inherent dialects, and the underlying IRs for various target chips. To address challenges such as the large architectural differences and varying granularity of hardware primitives in brain-inspired chips, BIVM leverages MLIR’s progressivity feature. This allows for the mixing of different abstraction levels and concepts (e.g. combining fine-grained instructions with coarse-grained computation based on the crossbar structure specific to certain back-ends), enabling software module reuse and reducing compiler development costs, ultimately leading to high productivity. In addition, the framework provides flexibility to combine various levels of compilation optimizations, including widely-used SNN-specific optimizations (e.g. exploring computing sparsity and improving parallelism) and low-level optimizations tailored to different back-ends, ensuring performance portability. The current BIVM prototype supports back-ends such as general-purpose processors (control-flow architecture), SNN accelerator chips (FPGAs) with a hybrid control-/data-flow architecture, and data-flow chip designs based on ReRAM (resistive random-access memory, a widely-used neuromorphic device). It can optimize and compile deep SNN and biological neural network simulation applications into executables tailored for these chips. Comprehensive testing and performance comparisons demonstrate the potential of this compilation framework in achieving high productivity, portability, and performance. |
| Key words: brain-inspired computing compilation framework brain-inspired computing chip |
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