| 摘要: |
| 嵌入式实时系统在安全关键领域变得越来越重要，其广泛应用于航空航天、汽车电子等具有严格时间约束的实时系统中.随着嵌入式系统的复杂度越来越高，在系统开发的早期设计阶段就需要对其可调度性进行分析评估.系统中的存储资源会对可调度性产生一定影响，在抢占式实时嵌入式系统引入缓存后，任务的最坏执行时间可能发生变化.因此，分析缓存相关抢占延迟对实时嵌入式系统的可调度性影响，一直以来是困扰大规模复杂系统架构设计的一个技术难题.提出一种面向软件架构级别、基于抢占调度序列的缓存相关抢占延迟计算方法，用来分析缓存相关抢占延迟约束下AADL （架构分析和设计语言）模型的可调度性.扩展了AADL关于存储资源架构设计的模型元素，来支持对缓存属性进行建模，提出一种基于模型构件进行抢占序列排序、缓存相关抢占延迟时间计算和被抢占任务最坏执行时间的估算方法，来对系统架构各功能构件在共享系统存储资源下系统的可调度性进行分析.还实现了分析缓存相关抢占延迟约束下的系统任务可调度性分析工具原型，并以某型飞机机载开放式智能信息系统为例，在航空电子系统架构设计中进行尝试，验证了该方法的在复杂系统设计中的对实时性分析的可行性. |
| 关键词: 软件架构分析与设计语言AADL 复杂嵌入式系统 缓存相关抢占延迟 资源约束的可调度性 |
| DOI：10.13328/j.cnki.jos.006243 |
| 分类号: |
| 基金项目:国家自然科学基金（61772423） |
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| On Schedulability Analysis of AADL Architecture with Storage Resource Constraint |
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LU Yin1, QIN Shu-Dong2, XI Le-Qi1, DONG Yun-Wei1
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1.School of Computer Science, Northwest Polytechnical University, Xi'an 710072, China;2.School of Software, Northwest Polytechnical University, Xi'an 710072, China
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| Abstract: |
| The embedded system has been wildly applied in real-time automatic control systems, and most of these systems are safety-critical. For example, the engine control systems in an automobile, and the avionics in an airplane. It is very important to verify the schedulability property of such real-time embedded system in its early design stages, so that to avoid unexpected loss for the debugging of architecture design frictions. However, it has been proved to be a tough challenge to evaluate the schedulability of a PSRT (preemptive-scheduling real-time) system, especially when taking the constraints of system resources into consideration. The cache memory build inside the processor is such a kind of exclusive-accessing resource that is shared by all the tasks deployed on the processor. In addition, the CPRD (cache-related preemption delay) caused by preemptive task scheduling will bring extra time to the execution time to all the tasks. Thus, the CPRD should be taken into consideration when estimating the WCET (worst case executing time) of tasks in a real-time system. A model-based architecture level schedulability evaluate and verification method, which is designed for priority based PSRT system, is proposed in this study, in order to do cache resource constrained, and CPRD related schedulability evaluation based on AADL system architecture model. In the first step, the study enhances the property set of AADL storage elements, so that to be compatible with cache memory properties in system architecture model constructing. Secondly, the study proposes a set or algorithms to:estimate the CPRDs of a task before it is completed; do system schedule simulation and construct the schedule sequence with the constraint of Cache resource and CPRDs involved; and WCET estimation of the tasks in such a CPRD considered, preemptive-scheduling execution sequence. Finally, methods mentioned above are implemented within a prototype software toolkit, which is designed to do system level schedulability evaluation and verification with CPRD constraints considered. The toolkit is tested with a use case of aircraft airborne open-architecture intelligent information system. The result shows that, compared with schedule sequence constructed without cache memory resource constraints, the WCET estimated for most tasks are extended, and sequence order is changed. In some extreme cases, when CPRD is taken into consideration, some tasks are evaluated to be incompletable. The test shows that the method and algorithms proposed in this study are feasible. |
| Key words: AADL complex embedded system cache related preemption delay resource constraint schedulability |
