| 摘要: |
| 现代晶体管技术在单芯片上集成多个处理器已经成为现实.近年来，随着多核处理器集成核数的不断增加，高速缓存的一致性问题凸显出来，已成为多核处理器的性能瓶颈之一，亟待解决.介绍了片上多核处理器一致性问题的由来.总结了多核时代高速缓存一致性协议设计的关键问题，综述了近年来学术界对一致性的研究.从程序访存行为模式、目录组织结构、一致性粒度、一致性协议流量、目录协议的可扩展性等方面，阐述了近年来缓存一致性协议性能优化的方向.对目前片上多核处理器缓存一致性协议设计中存在的问题进行了讨论，并指出了未来进一步研究的方向. |
| 关键词: 片上多核处理器 缓存一致性协议 性能优化 |
| DOI：10.13328/j.cnki.jos.005245 |
| 分类号: |
| 基金项目:国家自然科学基金（61300010，61300011）；中国科学院计算技术研究所计算机体系结构国家重点实验室开放课题（CARCH201404） |
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| Survey on Cache Coherence Protocol and Performance Optimization for Chip Multi-Processor |
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HU Sen-Sen, JI Wei-Xing, WANG Yi-Zhuo, CHEN Xu, FU Wen-Fei, SHI Feng
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High Performance Embedded Computation Laboatory, School of Computer Science and Technology, Beijing Institute of Technology, Beijing 100081, China
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| Abstract: |
| Modern-Day transistor technique enables the industry to integrate many cores on a single chip. As an increasing number of cores being integrated on a single chip, cache coherence has become an intractable issue as well as a bottleneck of performance. In this paper, the origin of cache coherence is carefully described. Further, the paper summarizes the key issue of cache coherence and reviews the study in this field a decade after entering the mulit-core era. From aspects of memory access, directory organization, coherence granularity, coherence traffic and scalability, the work on optimization of cache coherence in recent researches is also presented. Finally, the potential challenges in current coherence protocol and direction of future research are discussed. |
| Key words: chip multi-processor cache coherence protocol performance optimization |
