| 摘要: |
| 近年来，NAND闪存广泛应用于各类嵌入式系统.由于“异地更新”的限制，闪存中需要地址映射方法将来自文件系统的逻辑地址转换为闪存中的物理地址.随着闪存存储空间的日益增长，如何使地址映射表占用较小的内存而又不损失较多性能，成为一个重要的问题.基于需求的页级地址映射方法能够有效地解决这个问题，然而该方法会产生地址转换页操作的额外开销，影响系统性能.从基于需求的地址映射方法出发，从两方面进行优化：首先，为了减少转换页的频繁更新，提出了页级地址映射缓存技术以统一在闪存和内存中的地址映射信息的粒度；其次，设计了基于地址转换页的数据聚集技术.通过该技术，每个数据块在垃圾回收时产生的地址转换页的更新开销被降至最低.实验用一系列基准数据集并与之前代表性的工作进行比较，结果表明，优化的地址映射方法能够大量减少额外地址转换页的开销，并提高闪存存储系统的性能. |
| 关键词: 闪存 地址映射 存储系统 嵌入式系统 |
| DOI：10.13328/j.cnki.jos.004528] |
| 分类号: |
| 基金项目:国家自然科学基金（61170066, 61321491, 61003025）；国家高技术研究发展计划（863）（2011AA010103） |
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| Optimized Address Translation Method for Flash Memory |
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ZHANG Qi1, WANG Lin-Zhang1, ZHANG Tian1, SHAO Zi-Li2
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1.State Key Laboratory for Novel Software Technology (Nanjing University), Nanjing 210046, China;2.Department of Computing, The Hong Kong Polytechnic University, Hongkong 00853, China
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| Abstract: |
| NAND flash memory has been widely used in various embedded systems. Due to the “out-of-place” update constraints, a component of address translator in NAND flash management is needed to translate logical address from file system to physical address in NAND flash. With the capacity increase of NAND flash, it becomes vitally important to take small RAM print of the address mapping table while not introducing big performance overhead. Demand-based address mapping is an effective approach to solve this problem by storing the address mapping table in NAND flash (called translation pages) and catching mapping items on-demand in RAM. However, in such address mapping method, there exists extra many translation pages that may incur much performance overhead. This paper solves two most important problems in translation page management. First, to reduce frequent translation page updates overhead, a page-level caching mechanism is proposed to unify the granularity of the cached mapping unit in NAND flash and in translation caching. Second, to reduce the garbage collection overhead from translation pages, a translation page based data-assemblage strategy is designed to group data pages corresponding to the same translation page into one data block, reducing the cost of translation page update during garbage collection to the minimal level. The presented scheme is evaluated using a set of benchmarks and is compared to a representative previous work. Experimental results show that the new techniques can achieve significant reduction in the extra translation operations and improve the system response time. |
| Key words: flash memory address translation storage system embedded system |
