| 摘要: |
| 在许多关键应用中,计算机的高性能、低功耗和高可靠性是必须同时满足的要求.传统的软件容错技术频繁使用和比较分支指令检测错误,带来了巨大的性能和功耗的开销.提出了基于计算数据流模型的错误流模型,并设计了错误流压缩算法.在错误流压缩算法中,利用附加计算压缩了错误流的直径,显著减少了分支指令的数量,而总指令数不变.针对StreamIT提供的快速傅立叶变换测试程序,采用Wattch对错误流压缩算法进行模拟测试.实验结果表明,当循环参数n=225时,与传统的EDDI算法相比,使用错误流压缩算法可减少分支指令24%以上,IPC提高超过12%,同时,功耗减少了将近5%.给出的推算表明:在该实验中,如果内层循环体的存储指令数量为8,分支指令的减少可以达到43%以上. |
| 关键词: 软件容错 COTS 错误流模型 错误流压缩算法 分支指令 高性能 低功耗 |
| DOI： |
| 分类号: |
| 基金项目:Supported by the National High-Tech Research and Development Plan of China under Grant No.2002AA1Z2101 (国家高技术研究发展计划(863)) |
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| Efficient Fault Tolerant Compilation: Compress Error Flow to Reduce Power and Enhance Performance |
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GAO Long,YANG Xue-Jun
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| Abstract: |
| In many reliability-critical applications, computers are required to have higher performance, lower power dissipation and fault tolerance simultaneously. Traditional software fault tolerance uses a great deal of branch instructions to detect errors, thus brings great overhead in both performance and power dissipation. In this paper, an error flow model is suggested, and it is used to explain the algorithm of error flow compressing. In error flow compressing algorithm, branch instructions are reduced greatly, while total instructions remain the same. The simulated results on Wattch of FFT benchmark from project StreamIT show that compared with the traditional EDDI error detection algorithm, the EFC can reduce total branch instructions by over 24%, improve IPC by over 12%, and at the same time, reduce the power dissipation by nearly 5%, at loop parameter n=225. Further reasoning shows that the reduction of branch instructions can be as much as over 43% when there are 8 store instructions in the innermost iteration. |
| Key words: SIHFT (software implemented hardware fault tolerance) COTS error flow model error flow compressing algorithm branch instruction high performance low power dissipation |
