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| 基于三级存储阵列缓存高速数据包及性能分析 |
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王鹏1,2, 伊鹏2, 金德鹏1, 曾烈光1
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1.清华大学,电子工程系,北京,100084;2.解放军信息工程大学,电子工程系,河南,郑州,450002
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| 摘要: |
| 高速网络设备一般需要大容量高速数据包存储器来缓存收到的数据包.但以目前的存储器工艺水平很难实现这样的存储器,从而限制了整个网络的发展.提出一种新型的三级存储阵列结构可以成功解决数据包存储器的容量和带宽问题,理论上可以实现任意高速数据包的缓存.使用"最关键队列优先"算法完成对三级存储阵列的管理,证明了使用该算法能够保证数据包的无时延调度输出,并且其所需的系统规模最小,同时推导出系统规模的上、下限.最后给出三级存储阵列的一种可实现方案,从而使该结构易于硬件实现. |
| 关键词: 三级存储阵列 数据包存储 时延 |
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| 基金项目:Supported bythe National High-Tech Research and Development Plan of China under Grant No2001AAl21071(国家高技术研究发展计划(863)) |
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| Buffering High-Speed Packets with Tri-Stage Memory Array and Its Performance Analysis |
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WANG Peng,YI Peng,JIN De-Peng,ZENG Lie-Guang
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| Abstract: |
| High-Performance routers and switches need large throughput packet buffers to hold packets. However, the technique of commercially available memories is limited and can hardly fulfill this high throughput packet buffers. As a result, the development of networks is restricted severely. This paper presents a tri-stage memory array architecture to solve the problem, which can accomplish the arbitrary high-speed packet buffer theoretically. It is proved that the critical queue first algorithm can be applied as the memory management algorithm to get zero delay scheduling as well as minimum scale system. Furthermore, the design of hardware implementation architecture of the tri-stage memory array system is provided finally. |
| Key words: tri-stage memory array packet buffer delay |
