| 摘要: |
| VLSI模拟验证的一个关键问题是需要大量的模拟矢量来验证各种可能情况下设计的正确性.采用断言作为模拟验证的功能模型,提出和实现了一种基于断言的模拟矢量自动生成方法.针对要触发的断言,首先对设计进行化简,通过决策图模型将初始输入传播到断言,并将传播过程和断言条件一起转化成CLP约束,最后求解CLP约束生成模拟矢量.该方法的优势在于运用了字级(word-level)约束求解技术,能统一处理控制电路和数据通路间的数据传播,求解效率高;基于功能模型的模拟矢量生成技术,模拟矢量生成目标更明确;与动态加速技术相结合,使搜索过程效率更高;设计化简技术的运用使搜索过程计算复杂度只与断言有关.实验结果表明,该方法能快速找到并定位设计中的错误,生成模拟矢量效率更高. |
| 关键词: VLSI 断言 模拟矢量自动生成 |
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| 基金项目:Supported by the National Natural Science Foundation of China under Grant Nos.60303011, 90207019(国家自然科学基金);the National High-Tech Research and Development Plan of China under Grant No2002AA1Z1480(国家高技术研究发展计划(863) |
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| Assertion-Based Automatic Generation of Functional Vectors |
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LI Tun,GUO Yang,LI Si-Kun
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| Abstract: |
| Simulation-Based verification approaches need a large amount of test vectors for verifying the corner case of designs. This paper proposes a novel assertion-based automatic functional vectors generation method which takes assertion as the functional coverage metric. For the given assertion, the related design part is first extracted, and then the assertion property and the signal propagation process based on the DD model is converted to the CLP constraints; Finally, functional vectors are generated by solving the constraints. The advantage of this method is the combination of the program slicing based design extraction, the word-level SAT engine, and the dynamic search techniques. The method can deal with large designs and handle control and datapath design in a unified framework. Experimental results show that the method is efficient for finding the design errors and vectors generation. |
| Key words: VLSI assertion automatic functional vectors generation |
