| 摘要: |
| 提出了在多线程体系结构中通过降低执行频率有效减小功耗的理论模型和方法.首先研究识别可降频运行的线程的计算模型和降频因子的计算,然后给出在编译过程中基于对应用程序行为的分析,结合线程划分的低功耗编译优化算法和实现策略.该模型和方法可用于具有执行频率可动态调整的多处理器类多线程体系结构,既可开发TLP(thread level parallelism),又可有效减小功率消耗. |
| 关键词: 多线程 低功耗 编译优化 并行处理 计算机体系结构 |
| DOI： |
| 分类号: |
| 基金项目:国家高技术研究发展计划资助项目(2001AA111070) |
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| A Multithreaded Compiler Optimization Technology with Low Power |
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ZHAO Rong-cai,TANG Zhi-min,ZHANG Zhao-qing,Guang R. Gao
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| Abstract: |
| A theoretic model and method is proposed to decrease power consumption effectively by reducing execution frequency on multithreaded architecture in this paper. At first, the computation model is studied to recognize the thread which can be executed at lower frequency, and the factor is computed to slow down the frequency. Then, an algorithm and policy of compiler optimization combining with thread partition for low power is given based on the analysis of application program. This model and method can be used to exploit TLP(thread levelparallelism)and decrease the power consumption effectively for the multithreaded multiprocessor architecture with scalable execution frequency. |
| Key words: multithreading low power compiler optimization parallel computing computer architecture |
