| 摘要: |
| 该文主要讨论高级综合系统RTL(register transfer level)级综合结果正确性验证策略的确 定及验证系统设计中DFG(data flow graph)逆向获取算法的设计与实现.算法主要包括4个处 理阶段：FSM(finite state machine)动态分析及控制输出获取；FSM当前状态下数据通道有 效元件分析；数据通道结构到DFG操作结点转换；DFG结点间数据依赖关系分析、共享寄存器 变量分离及有向边的形成. |
| 关键词: 高级综合,硬件设计验证. |
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| 分类号: |
| 基金项目:本文研究得到国家自然科学基金和国防预研基金资助. |
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| Research on Data Flow Graph Extracting Technology for Verificat ion of High Level Synthesis Correctness |
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XU Qing-ping,LIU Ming-ye,SONG Han-tao
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| Abstract: |
| To verify the correctness of the RTL(register transfer level) result got from th e high level synthesis, an algorithm of DFG(data flow graph) invert extracting i s designed and realized in this paper. Four sections are included in this algori thm: analyze FSM(finite state machine) dynamically and obtain control signal; se arch the active component for current states of FSM and convert the operate note of DFG from the structure of data path; analyze the relationship between the no tes of DFG, separate the variables sharing the same register. |
| Key words: High level synthesis, hardware design verification. |
