| 摘要: |
| 本文扼要地论述了高级综合的过程和其中控制信息的提取与变换，实现了控制流综合与数据流综合结果的衔接，并对FPGAXilinx设计库单元映射成工艺相关的ASIC，直至生成FPGA器件． |
| 关键词: FSMD 调度 分配 有限状态自动机 时序逻辑综合 |
| DOI： |
| 分类号: |
| 基金项目:本文研究得到国家自然科学基金资助. |
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| EXTRACTION AND SYNTHESIS OF CONTROL INFORMATION IN HIGH LEVEL SYNTHESIS |
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YE Meilong,ZHANG Dongxiao,HENG Donghui,JIN Yi
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| Abstract: |
| The authors discuss concisely, the process of high level synthesis and the extraction and transformation of control information generated in the said process. The authors also discuss the methodology of linking the result of data flow synthesis and that of control flow synthesis as well as the mapping to technology-dependent ASIC based on Xilinx FPGAs. |
| Key words: FSMD scheduling allocation finite state machine sequential logic synthesis |
