| 摘要: |
| 本文介绍我们研究开发的模块硅编译专家系统——SCES,它由若干个具有公共黑板结构,协同工作的领域专家系统群体构成。SCES具有开放的推理调度系统,广泛使用演绎CAD数据库(dCADB)和逻辑演绎方法,根据输入的模块联结的描述和设计的要求(例如带负荷后的时间延迟,引线排列,模块芯片的长宽比等),通过逻辑网络拓扑结构修正、逻辑功能级和版图级的自动设计,以逐步求精的方式,达到给定的设计要求。最后输出模块的逻辑图、版图;生成记录设计过程和结果的各种dCADB,给出模块各节点逻辑值推演结果、逻辑链时间延迟推演结果以 |
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| 基金项目:863支持;; 七五国家重点攻关项目 |
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| MODULE SILICON COMPILATION EXPERT SYSTEM-SCES |
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Yang Qiaolin
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| Abstract: |
| This paper presents a module silicon compilation expert system--SCES developed by us. SCES consists of a set of cooperating expert systems with common blackboard structures and is featured by performing topological modification, using widespreadly deducing CAD database (dCADB), logical reduces, rule_based programming and an open inference schedule system. SCES takes specifications (chip dimension rate, cell delays and pad arrangements) from input file, performs topological modifications, logical and layout automatic design,sets up dCABs of design results,outputs the logic drawing,layout and circuit SPICE format file including parasitic parameters of interconnections. |
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