| 引用本文: | 罗法蕾,王苫社,马俊铖,马思伟,高文.面向CPU-GPU平台的HEVC编码器优化.软件学报,2015,26(S2):239-246 |
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| 面向CPU-GPU平台的HEVC编码器优化 |
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罗法蕾1,2, 王苫社3, 马俊铖3, 马思伟3,4, 高文1,3,4
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1.中国科学院计算技术研究所, 北京 100190;2.中国科学院大学, 北京 100049;3.北京大学数字媒体所 & 协同创新中心, 北京 100871;4.北京大学深圳研究生院, 广东深圳 518055
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| 摘要: |
| 针对CPU-GPU平台提供了一种能显著降低高效视频编码(high efficiency video coding,简称HEVC)复杂度的优化方案.根据编码器的复杂度分布及不同模块的特点,针对帧内预测、帧间预测以及环路滤波分别进行了优化.在帧内预测中,基于相邻编码单元(coding unit,简称CU)之间的相关性,提出了一种CU的深度决策方法以及一种减少率失真优化(RDO)的模式数量的方法,降低了帧内编码的复杂度.在帧间预测中,提出将耗时最大的运动估计模块完善在图形处理单元(GPU)上,通过中央处理单元(CPU)和GPU的流水线工作获得了明显的加速,并基于预测残差的能量提出了一种编码单元提前终止划分的方法,有效降低了帧间编码复杂度.在环路滤波中,提出了一种GPU端的自适应样本点补偿(sample adaptive offset,简称SAO)参数决策方法及去块滤波方法,有效分担了CPU端的复杂度.上述优化实现在HM16.2上,实验结果表明,提出的优化方案可以获得高达68%的编码复杂度节省,而平均性能损失仅为0.5%. |
| 关键词: 高效视频编码 图形处理单元 帧内编码 帧间编码 环路滤波 |
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| 基金项目:国家高技术研究发展计划(863)(2015AA015903);国家自然科学基金(61322106, 61272255);深圳市孔雀计划;北京市优秀博士学位论文导师奖资助项目(20128000103) |
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| HEVC Encoder Optimization for CPU-GPU Platform |
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LUO Fa-Lei1,2, WANG Shan-She3, MA Jun-Cheng3, MA Si-Wei3,4, GAO Wen1,3,4
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1.Institute of Computing Technology, The Chinese Academy of Sciences, Beijing 100190, China;2.University of Chinese Academy of Sciences, Beijing 100049, China;3.Institute of Digital Media & Cooperative Medianet Innovation Center, Peking University, Beijing 100871, China;4.Shenzhen Graduate School, Peking University, Shenzhen 518055, China
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| Abstract: |
| This paper provides a comprehensive optimization strategy aiming at reducing the complexity of high efficiency video coding (HEVC) encoder with CPU-GPU cooperation. Based on the computational complexity distribution of HEVC encoder and characteristics of different modules and coding tools, intra coding, inter coding and in-loop filtering are collaboratively optimized. For intra coding, based on the correlation between neighboring coding units (CUs), depth range of CU is predicted and the number of candidates in intra mode candidate set for RDO (rate distortion optimization) is cut down, to avoid unnecessary computations. For inter coding, the most time consuming module, motion estimation (ME), is implemented with the collaboration of CPU and GPU in pipeline. Based on the energy of prediction residuals, an early termination scheme of CU splitting is proposed in this paper. For in-loop filtering, GPU based sample adaptive offset (SAO) parameter decision scheme and GPU based deblocking scheme are proposed to further reduce the coding complexity on CPU. The overall optimization scheme is implemented on the HM 16.2 platform, and experiments demonstrate that the proposed optimization scheme can reduce over 68% of the coding complexity of HEVC encoder, with only 0.5% performance loss in average. |
| Key words: high efficiency video coding graphic processing unit intra coding inter coding loop filtering |
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