Power Estimation Model on Multi-Core Platforms
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    Abstract:

    Accurate power consumption estimation can provide a significant guidance for OS scheduling and software/hardware power efficiency optimization. Previous researches have indicated that power consumption can be estimated by monitoring the related hardware events inside the CPU, such as instruction submission times and caches access times. However, those models which are based on hardware are not able to provide accurate results; they often come with an error over 5%. This study first analyzes the hardware events provided by the CPU, then chooses a set of events that are closely related to power consumption, and finally uses step by step multi-element linear regression analysis to build our run-time estimation model. This model is not related to any applications and can be directly transformed into the platforms that support SMT. The model is verified with the two benchmark suites PARSEC and SPLASH2, resulting in estimated errors of 3.01% and 1.99% respectively. To address the issue of high time consuming in modeling, an optimization scheme with two-step cluster is also presented in this article. The proposed estimation model can serve as a foundation for the intelligent power consumption perception systems that dynamically balance power assignment and smooth peak power consumption at run-time.

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刘辛,沈立,苏博,王志英.多核处理器的功耗估算模型.软件学报,2015,26(7):1840-1852

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History
  • Received:May 07,2014
  • Revised:July 29,2014
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  • Online: July 02,2015
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