HEVC Encoder Optimization for CPU-GPU Platform
DOI:
Author:
Affiliation:

Clc Number:

Fund Project:

  • Article
  • |
  • Figures
  • |
  • Metrics
  • |
  • Reference
  • |
  • Related
  • |
  • Cited by
  • |
  • Materials
  • |
  • Comments
    Abstract:

    This paper provides a comprehensive optimization strategy aiming at reducing the complexity of high efficiency video coding (HEVC) encoder with CPU-GPU cooperation. Based on the computational complexity distribution of HEVC encoder and characteristics of different modules and coding tools, intra coding, inter coding and in-loop filtering are collaboratively optimized. For intra coding, based on the correlation between neighboring coding units (CUs), depth range of CU is predicted and the number of candidates in intra mode candidate set for RDO (rate distortion optimization) is cut down, to avoid unnecessary computations. For inter coding, the most time consuming module, motion estimation (ME), is implemented with the collaboration of CPU and GPU in pipeline. Based on the energy of prediction residuals, an early termination scheme of CU splitting is proposed in this paper. For in-loop filtering, GPU based sample adaptive offset (SAO) parameter decision scheme and GPU based deblocking scheme are proposed to further reduce the coding complexity on CPU. The overall optimization scheme is implemented on the HM 16.2 platform, and experiments demonstrate that the proposed optimization scheme can reduce over 68% of the coding complexity of HEVC encoder, with only 0.5% performance loss in average.

    Reference
    Related
    Cited by
Get Citation

罗法蕾,王苫社,马俊铖,马思伟,高文.面向CPU-GPU平台的HEVC编码器优化.软件学报,2015,26(S2):239-246

Copy
Share
Article Metrics
  • Abstract:
  • PDF:
  • HTML:
  • Cited by:
History
  • Received:May 15,2015
  • Revised:October 12,2015
  • Adopted:
  • Online: January 11,2016
  • Published:
You are the firstVisitors
Copyright: Institute of Software, Chinese Academy of Sciences Beijing ICP No. 05046678-4
Address:4# South Fourth Street, Zhong Guan Cun, Beijing 100190,Postal Code:100190
Phone:010-62562563 Fax:010-62562533 Email:jos@iscas.ac.cn
Technical Support:Beijing Qinyun Technology Development Co., Ltd.

Beijing Public Network Security No. 11040202500063