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DOI:
Journal of Software:2009.20(zk):15-22

CPU/FPGA混合架构上的硬件线程加速方法
陈天洲,严力科,胡威,马吉军
(浙江大学 计算机科学与技术学院,浙江 杭州 310027)
Hardware Thread Accelerating Method Based on CPU/FPGA Hybrid Architecture
CHEN Tian-Zhou,YAN Li-Ke,HU Wei,MA Ji-Jun
()
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Received:July 01, 2008    Revised:April 02, 2009
> 中文摘要: CPU/FPGA混合架构是可重构计算的普遍结构,为了简化混合架构上FPGA的使用,提出了一种硬件线程方法,并设计了硬件线程的执行机制,以硬件线程的方式使用可重构资源.同时,软硬件线程可以通过共享数据存储方式进行多线程并行执行,将程序中计算密集部分以FPGA上的硬件线程方式执行,而控制密集部分则以CPU上的软件线程方式执行.在Simics仿真软件模拟的混合架构平台上,对DES,MD5SUM和归并排序算法进行软硬件多线程改造后的实验结果表明,平均执行加速比达到了2.30,有效地发挥了CPU/FPGA混合架构的计算性能.
Abstract:The CPU/FPGA hybrid architecture is a popular reconfigurable computing architecture. In order to ease the use of FPGA, a hardware thread approach is proposed, and a hardware thread executing mechanism is designed to make use of the reconfigurable resources. Software thread and hardware thread can be executed in parallel while computation-intensive tasks are assigned to hardware threads and control-intensive tasks are assigned to software threads. Simics simulator is adopted to simulate a hybrid architecture platform, on which software and hardware multithreading DES, MD5SUM and MergeSort algorithms are evaluated. The results show that the average speedup is 2.30, and it proves that the approach explored the performance of CPU/FPGA hybrid architecture efficiently.
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基金项目:Supported by the National Natural Science Foundation of China under Grant No.60673149 (国家自然科学基金); the National High-Tech Research and Development Plan of China under Grant No.2007AA01Z105 (国家高技术研究发展计划(863)) Supported by the National Natural Science Foundation of China under Grant No.60673149 (国家自然科学基金); the National High-Tech Research and Development Plan of China under Grant No.2007AA01Z105 (国家高技术研究发展计划(863))
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陈天洲,严力科,胡 威,马吉军.CPU/FPGA混合架构上的硬件线程加速方法.软件学报,2009,20(zk):15-22

CHEN Tian-Zhou,YAN Li-Ke,HU Wei,MA Ji-Jun.Hardware Thread Accelerating Method Based on CPU/FPGA Hybrid Architecture.Journal of Software,2009,20(zk):15-22